PROJECTS

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1.A New Compact SD2 positive integer Triangular Array Division Circuit

2.Building an AMBA AHB Compliant Memory Controller

3.A New VLSI Architecture of parallel multiplier–accumulator based on radix-2 Modified Booth Algorithm

4.Implementation of low cost Bist circuit for Public Key Cryptocores

5.Initialization-based Test Pattern generation for Asynchronous circuits

6.A Mixed style multiplier architecture for low dynamic and leakage power dissipation

7.Design of Cordic Core Algorithm in FPGA

8.Design a low power Booth Multiplier in FPGA

9.Implementation of Two Fish Cryptographic Algorithm

10.Implementation of phase shift keying (QPSK,BPSK)

11.Implementation of MAC Unit

12.Design of Viterbi decoder

13.Design of Uart Transmitter module and Uart Receiver module

14.VHDL code for 3*3 Matrix Multiplication

15.Uart module for Real Time Application

16.An Area-efficient Universal cryptography processor for Smart cards

17.Implementations of Quadrature Amplitude Modulation technique

18.Design and simulation of memory blocks of RAM and ROM implementation in VLSI

18.Design and simulation of memory blocks of RAM and ROM implementation in VLSI

19.Design of low power fir filter.

20.Design and implementation of reed solomon encoder in hdl.

21.Design and implementation of reed solomon decoder in hdl.

22.Design of 32-bit pci-x bus interface ip core and implementation on fpga board.

23.Design and implementation of rs-232 system controller.

24.Design of 16-bit micro controller.

25.Design and implementation of atmel avr at90s1200 standard risc micro controller.

26.Design of time slot interchange digital switch.

27.Implementation of cyclic redundancy checker for error detection and correction.

28.Design of 8-bit 2-dimentional discrete cosine transform.

29.Wireless healthcare system

30.Company security reporting system

EZES279 VLSI Implementation of a Cost-Efficient Micro Control Unit With an Asymmetric Encryption for Wireless Body Sensor Networks

EZES280 Overloaded CDMA Crossbar for Network-On-Chip

EZES281 Dual-Quality 4:2 Compressors for Utilizing in Dynamic Accuracy Configurable Multipliers

EZES282 Energy-Efficient VLSI Realization of Binary64 Division With Redundant Number Systems

EZES283 Design of Efficient BCD Adders in Quantum Dot Cellular Automata

EZES284 Area-Efficient Architecture for Dual-Mode Double Precision Floating Point Division

EZES285 Design of a Real-Time ECG Filter for Portable Mobile Medical Systems

EZES286 Lower Bound Analysis and Perturbation of Critical Path for Area-Time Efficient Multiple Constant Multiplications

EZES287 High-performance VLSI architectures for M-PSK modems

EZES288 Hardware/Software Approach to Designing Low-Power RNS-Enhanced Arithmetic Units

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